1. Field of the Invention
This invention relates to semiconductor devices and more specifically to MOS field effect transistors.
2. Prior Art
MOSFET devices are well known in the prior art and are described in many patents and publications. One such source of prior art practice is a book "MOS Integrated Circuits" (1972) edited by William M. Penney and Lillian Lau.
The structure of a MOSFET device, as disclosed by the prior art, includes a monocrystalline semiconductor region (e.g., substrate wafer) with a pair of closely spaced regions on the surface, opposite in conductivity type as compared with the substrate, called the source and the drain. A gate electrode, made either of an appropriate material, such as, a metal, or a semiconductor material, removed from the wafer by a layer of insulating material such as silicon oxide or nitride or a combination thereof which insulating material covers the area between the source and the drain. Various maskings, oxidation steps and metalizations are used in the process of forming the device elements and making contact with them. The impedance existing between the source and drain elements is controlled by the potential applied to the gate element.
Certain difficulties have been noted in the prior art devices which have been eliminated by the present invention. For example, in prior art devices "junction spiking" is a very common defect. This defect comes about because of the preferential etching which occurs along the 100 plane in a monocrystalline silicon wafer (hereinafter referred to as "100 plane silicon"). The 100 plane silicon is often used in n-channel MOS devices although 111 plane silicon may be employed. (In 111 plane silicon the preferential etching tends to occur in a lateral plane.) The preferential etching defect results from the processing temperatures commonly used after metalization (e.g., aluminum), which enables material from the substrate (e.g., silicon) to diffuse from the contact area of the substrate into the metalization and conversely the metalization flows to fill the voids in the substrate (e.g., contact areas of substrate). Thus, the substrate material dissolves in the metalization. Further, the metalization (e.g., aluminum) often dissolves the substrate material (e.g., silicon) in a preferential manner that produces metal penetration much further into the substrate than would be the case if the dissolution of the substrate and the subsequent penetration by the metalization were isotropic (radiating equally in all directions). If the metalization penetrates through the junction it often results in a short of the junction. This phenomena is known in the industry as junction spiking. As will be described later, preferential etching does not tend to occur in the invented device. In addition, the junctions can be preferentially deepened in the vicinity of the contacts. Both of these improvements result in a device that is much less prone to junction spiking.
An important use of MOS devices is for dynamic memory purposes. In this application, information may be stored in the cell for a short period of time due to the effect of minority carrier lifetime in the source and drain elements and associated effective capacitance. In prior art devices the storage time available is often quite short and very sensitive to the presence of certain impurities in the semiconductor material. Because of the greatly increased minority carrier lifetime of a cell employing the invention, the yields of parts with an acceptable storage time can be significantly increased. Alternatively, it is possible to maintain the present yields and produce parts having a substantially longer refresh cycle. Thus, when circuits employing the invention are in use, it is possible that such circuits will employ a much smaller percentage of available system time to restore and maintain the stored information. In substance, a dynamic cell is, without structural addition or the addition of components, made to approach the performance of a static cell which generally requires many more components. This result is attained with a number of other advantages incident thereto. For example, it is possible in an n-channel MOS device to deepen the junctions in the vicinity of the contacts to the source and drain without making the source and drain equally deep at portions directly adjacent the gate. Thus, low gate to drain capacitance may be obtained enabling high-speed performance while permitting simple metalization. Also, the metal cracking problem is simultaneously provided for and greater flexibility and tolerance are enabled in the metalization.